1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, particularly to a method for fabricating a semiconductor device comprising a device formed on a semiconductor substrate and an electrode extended from the device.
2. Description of the Related Art
As advanced information-intensive society has been developed in recent years, a computer for processing information at higher speed and communication in a short wavelength region for transferring more information are requested. To meet these requests, an LSI operating at higher speed is necessary and also a quickly-operating transistor constituting the LSI is necessary.
The inventor of the present invention et al. propose a self-aligning high-speed bipolar transistor in the following document.
[1] S. Nakamura et al., International Electron Devices Meeting pp.445-448, 1992
FIG. 1 shows a sectional view of a self-aligning bipolar transistor formed by using the prior art.
In FIG. 1, an N.sup.+ -type semiconductor buried layer 101 and N.sup.- -type semiconductor layer 102 are formed on a single-crystalline semiconductor substrate 100. The N.sup.- -type semiconductor layer 102 and a collector contact region 103 are enclosed by a field insulating film 104. Moreover, P-type external base layer 105 and P-type internal base layer 106 which constitute a bipolar transistor are formed on the N.sup.- -type semiconductor 102 and an N-type emitter layer 107 is formed above the internal base layer 106. Furthermore, a base extending electrode 108 made of a polycrystalline semiconductor containing impurities is connected to the external base layer 105. The base extending electrode 108 is extended onto a field oxide film 104 along a thin insulating film 109 formed on the surface of the N.sup.- -type semiconductor layer 102.
A metallic base electrode 112 is formed on the base extending electrode 108 on the field oxide film 104 through an opening 111 formed on an interlayer insulating film 110 covering the base extending electrode 108. A side wall 113 made of an insulating material is formed on a side surface of the base extending electrode 108 closer to an emitter layer 107 and moreover, an emitter extending electrode 114 made of polycrystalline semiconductor containing impurities and a metallic emitter electrode 115 are formed on the emitter layer 107.
The N.sup.- -type semiconductor layer 102 under the base layers 105 and 106 serves as a collector layer. In the collector contact region, an N.sup.+ -type collector extending layer 116 is formed at a depth reaching the buried layer 101 by introducing donor to the N.sup.- -type semiconductor layer 102. Moreover, a collector electrode 118 is formed on the collector extending layer 116 through an opening 117 of the interlayer insulating film 110.
The outside base layer 105 and the emitter layer 107 are formed in self-alignment due to diffusion of impurities in the extending electrodes 108 and 114 on the layers 105 and 107. The internal base layer 106 is formed in self-alignment by means of ion implantation.
Several methods for obtaining a bipolar transistor with the above structure are known. Important features of the structure are summarized into the following four points.
That is, (1) in the central base region of an active area demarcated by a thick field insulating film, (2) an insulating film, conducting film, and opening passing through the insulating film are formed on a semiconductor substrate, (3) a conductor layer or semiconductor layer for bringing the conducting film into contact with the semiconductor substrate is formed on the inner wall of the opening or at a portion adjacent to the opening, and (4) an emitter extending conducting film is formed which is insulated from the conductor layer or semiconductor layer and contacts the semiconductor substrate through the opening.
For the "conductor layer or semiconductor layer for connecting the conducting film with the semiconductor substrate" in the above point (3), the fabrication method depends on the art. However, the structure is almost the same.
To operate a bipolar transistor or MOS transistor at a high speed, it is indispensable to decrease the parasitic capacitance.
The above transistor according to the prior art can be operated at a high speed because the base layers 105 and 106 and the emitter layer 107 are finely formed in self-alignment and thereby the parasitic capacitances between the base and emitter and between the base and collector are decreased.
Moreover, to meet the request for higher speed, it is necessary not only to decrease the junction capacitance between the base and collector by decreasing the base area but to decrease the total parasitic capacitance between the base and collector by decreasing the parasitic capacitance between the N.sup.- -type semiconductor layer serving as a collector layer and the base extending electrode.
The parasitic capacitance between the base and collector is determined by the interval between the base extending electrode 108 and the collector layer (102) and the permittivity of an insulating material between the electrode 108 and the collector layer (102).
However, as the interval is increased, the position of the base extending electrode 108 rises and the aspect ratio of the opening where the emitter extending electrode 114 is formed is higher. Therefore, the overall lengths of the emitter extending electrode 114 and base extending electrode 108 resultingly increase, the resistances of them increase, a parasitic resistance which is another important factor to obtain at high speed increases, and thereby a transistor operation speed is decreased.
To decrease the parasitic capacitance between the base extending electrode 108 and collector layer (102) without increasing the interval between them, it is preferable to set an insulating material with a small permittivity between them.
For example, it is considered to form a space between them in order to decrease the parasitic capacitance between electrodes as disclosed in the official gazette of Japanese Patent Laid-Open No. Hei. 1-137651.
The method for forming the space according to the official gazette comprises the steps of forming an insulating support portion 131 on a lower interconnection electrode 130 as shown in FIG. 2A and then filling a portion serving as a space with SOG (spin on glass) 132 as shown in FIG. 2B, and thereafter forming an upper interconnection electrode 133 as shown in FIG. 2C and moreover removing the SOG 132 from the space by means of wet etching as shown in FIG. 2D. In FIG. 2, symbol 134 represents a substratum insulating film.
However, unlike the above interconnection electrode, the extending electrode of the bipolar transistor having the structure shown in FIG. 1 constitutes a part of the transistor and moreover the transistor has a very small area. Therefore, because only the art disclosed in the above official gazette is insufficient and a method for fabricating a semiconductor device suited to fabricate a self-aligning transistor is necessary.
The self-aligning transistor includes a MOS transistor and a static induction transistor in addition to the bipolar transistor.